1. Field of the Invention
The invention relates to an electrical component having a sensor and/or actuator chip, in particular a CMOS chip, that has a substrate on which a passivation layer and at least one structure that has at least one active surface area for a sensor and/or actuator are located, and the chip is surrounded by an encapsulation that has at least one opening that forms an access to the active surface area, of which at least one is present, and to the passivation layer, and in the opening the chip has an interaction surface that extends, at least in some areas, over the passivation layer and the active surface area and that in the operating position is in contact with a liquid or viscous medium, and a first electrical insulation layer is provided between the passivation layer and the substrate, and a first conductor track layer is located in some areas between the passivation layer and the first insulation layer, and a second electrical insulation layer is provided between the first insulation layer and the substrate, and a second conductor track layer is located between the first insulation layer and the second insulation layer, and at least one of the conductor tracks is connected to the sensor and/or actuator structure.
2. Description of Related Art
An electrical component of this type is known from actual practice. It has a CMOS chip with a semiconductor substrate into which an ion-sensitive field effect transistor (ISFET) is integrated. The sensor has an active surface area that is configured as a gate electrode and that can be brought into contact with a liquid medium in order to detect ions contained in this medium. A plurality of conductor track layers made of aluminum, in which the conductor tracks and/or sections of conductor tracks extend, are located on the substrate. Conductor track sections of conductor tracks that extend across to a plurality of conductor track layers are connected to each other by means of through-contacts. An electrical insulation layer is provided between each of the conductor track layers as well as between the lowermost conductor track layer, which is located closest to the substrate, and the substrate. A passivation layer is located as a cover layer on the stack of layers comprising the conductor track layers and the insulation layers. The circuit tracks connect the drain and source of the ISFET with bond pads that are spaced apart from the drain and source and are located on the surface of the CMOS chip.
The CMOS chip is encapsulated with a plastic casting compound that is in close contact with the chip and that has an opening that is connected to the active surface area and into which the liquid medium may be filled. Thus, the medium [typo in German] comes into contact with the chip at an interaction surface that extends across a part of the passivation later and the active surface area. The conductor track layers and the insulation layers in each case extend into the area of the chip that is covered by the interaction surface. The passivation layer and the insulation layers serve as corrosion protection for the circuit track layers in order to prevent the circuit track layers from coming into contact with the liquid medium. However, it has been found in actual practice that the passivation layer only provides limited corrosion protection for the conductor track layers, and that the chips only have a relatively short service life when the opening is filled with a liquid or viscous medium. If a conductor track comes into contact with the medium, for example due to a defect in the passivation layer, the entire chip can fail.
A semiconductor chip that has a silicon substrate on which an array having 16 approximately rectangular electrodes is disposed as disclosed in F. Faβbender et. al., Optimization of Passivation Layers for Corrosion Protection of Silicon-Based Microelectrode Arrays, Sensors and Actuators B 68 (2000), p. 128-133. The electrodes are connected to bond pads by means of conductor tracks located in a single conductor track layer. The conductor track layer is covered by a passivation layer. When the chip is manufactured, a silicon dioxide layer is generated on the semiconductor substrate with the aid of a heat-treating process. Trench-like recesses are imparted in this layer at the locations at which the conductor tracks will later be present. A metal that forms the circuit tracks is deposited in these recesses. The recessed arrangement of the conductor tracks in the silicon dioxide layer causes the chip to have an essentially flat surface. The purpose of these is to prevent mechanical stresses in the passivation layer, which can lead to cracks through which an analyte that is to be analyzed using the electrodes can come into contact with the conductor track layer and can cause corrosion on the conductor track layer. The corrosion resistance of the chip can be improved with this measure, and thus the service life of the chip can be extended. However, placing the trenches in the silicon dioxide layer located on the substrate results in a substantial additional expense in the manufacturing of the chip, in particular with a CMOS process.
The object of the invention is therefore to provide an electrical component of the type referred to above that can be manufactured in a cost-effective manner using the standard semiconductor manufacturing processes but that permits good corrosion resistance as well as long service life.